FAN4800AUN【PDF 14/19 页】IC PWM/PFC CTLR COMBO 16-MDIP

?2011 Fairchild Semiconductor Corporation

www.fairchildsemi.com

FAN4800AU/CU " Rev. 1.0.1

14

V

RM S

V

R M S -U V P

2

1

R

M

S

V

?/DIV>

7.94

Figure 29. Modulation Gain Characteristics

V

IN

I

L

V

E A

Figure 30. Line Feed-Forward Operation

To sense the RMS value of the line voltage, averaging

circuit with two poles is typically employed, as shown in

Figure 28. Notice that the input voltage of the PFC is

clamped at the peak of the line voltage once the PFC

stops switching because the junction capacitance of the

bridge diode is not discharged, as shown in Figure 31.

Therefore, the voltage divider for VRMS should be

designed considering the brownout protection trip-point

and minimum operation line voltage.

PFC Runs

PFC Stops

V

IN

V

RMS

Figure 31. V

RMS

According to the PFC Operation

The rectified sinusoidal signal is obtained by the current

flowing into the IAC pin. The resistor R

IAC

should be

large enough to prevent saturation of the gain

modulator, calculating as:

A

G

R

V

M A X

IA

M IN

LINE

m

140

2

<

?/DIV>

(3)

where V

LINEMIN

is the line voltage that trips brownout

protection, G

MAX

is the maximum modulator gain

when V

RMS

is 1.08 V (which can be found in the

datasheet), and 140 礎 is the maximum output

current of the gain modulator.

Current Control of Boost Stage

The FAN4800AU/CU employs two control loops for

power factor correction, as shown in Figure 32: a

current-control loop and a voltage-control loop. The

current-control loop shapes inductor current as shown

in Figure 33 based on the reference signal obtained at

the IAC pin calculated as:

M

A

M

L

R

G

I

R

I

R

?/DIV>

=

?/DIV>

=

?/DIV>

1

(4)

IS E N S E

IA C

V R M S

V E A

IE A

R

M

R M

R

R M S 1

R

R M S 2

R R M S 3

C

R M S 1

C R M S 2

R I A C

I

A C

V

I N

I

L

R

C S 1

R

F 1

C

F 1

I M O

R

I C

C I C 1

C

I C 2

+

-

D riv e

lo g ic

O P F C

2 .5 V

R

V C

R

V C 1

R

V C 2

F B P F C

R

F B 1

R

F B 2

V

O

V R E F

Figure 32. Gain Modulation Block

I

A C

I

L

M

O

R

Figure 33. Inductor Current Shaping

The current-control feedback loop also has a pulse-by-

pulse current limit comparator that forces the PFC

switch to turn off until the next switching cycle if the

ISENSE pin voltage drops below -1.3 V.

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